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Feature Req.: Mode Adaption Header for RAW BBFrame support

Feature Req.: Mode Adaption Header for RAW BBFrame support

Postby newsy » Wed Aug 10, 2016 4:56 am

Hi,

as this is the "professional" tuner card, I'm wondering, if TBS has interest to support also some professional features like some other competitor.
In DVB-S2 standard "Generic Continuous mode" is defined and it should be possible to receive these streams also with the new TBS card somehow.
The stv0910 demod can be set to BBFrame output, however as there's no sync byte in the BBFrames, the detection of the BBFrame start is very faulty.
As the stv0910 demod is able to indicate the start of a BBFrame, the media bridge could analyze it and put some layer around it.
As the Media Bridge of this new model is FPGA based, this should be feasible now.

There are also 2 types of encapsulatin layers for BBFrames: L2 and L3 frames according to http://satlabs.org/pdf/sl_561_Mode_Adap ... t_v1.3.pdf

The 2 byte long L2 should be sufficient for reliably detecting the Start of a BBFrame: 1 Byte Sync, 1 Byte Acm Command

kind regards

Newsy
newsy
 
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Re: Feature Req.: Mode Adaption Header for RAW BBFrame suppo

Postby luchy » Wed Aug 10, 2016 12:02 pm

hi
do you use linux or windows system? if you are using it under windows please test with the following link driver.
https://my.pcloud.com/publink/show?code ... kJ2zisYjyX
best regards,
luchy
 
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Re: Feature Req.: Mode Adaption Header for RAW BBFrame suppo

Postby newsy » Wed Aug 10, 2016 1:22 pm

thank you for the link, but I'm on the linux world.
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Re: Feature Req.: Mode Adaption Header for RAW BBFrame suppo

Postby crazycat » Wed Aug 10, 2016 11:43 pm

newsy Wrote:As the Media Bridge of this new model is FPGA based, this should be feasible now.

Ecp3 is simple FPGA, implement only PCI-E bridge + TS and I2C-buses. For handling bbframe traffic need more complex hardware and software part, like used in dektec dta-2137c. Anyway this beyond BDA and V4L DVB framework.
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Re: Feature Req.: Mode Adaption Header for RAW BBFrame suppo

Postby newsy » Sun Aug 21, 2016 8:01 pm

Hi crazycat,

as I've got a simplified view on this,
can you please explain more in detail, what problems occur when trying to receive BB frames with ecp3 fpga?
The signalling to detect the start of a BBframe would not work, but nevertheless shouldn't it be possible to transmit the complete BBFrames via TS fifo to Ecp3 and then to pcie bus? Or is there any limit in maximum frame length?
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